In the field of semiconductor device manufacturing, transistors are generally manufactured by front end of line (FEOL) technologies. High-k metal gate (HKMG) transistors have been widely used because of their superior performance over conventional poly-based transistors. Various processes have been developed to manufacture HKMG transistors including, among others, a gate-last replacement metal gate (GL-RMG) process, which is considered as one of the most promising processes.
Generally, after structure of a transistor is formed, conductive contacts are formed to connect to the source, drain, and/or gate of the transistor in order to make the transistor fully functional. With the continuing scaling down in device dimension in integrated circuitry, real estate for forming conductive contacts is also becoming smaller and smaller. As a result, contacts that are borderless to the device, which generally requires less real estate, are making their way into logic structures such as transistors.
However, despite some demonstrated feasibility of forming borderless contacts for transistors that are made by non-replacement metal gate (non-RMG) processes, technical difficulty still exists in integrating approaches that are used in a non-RMG process into a RMG process. For example, when applying an non-RMG approach to form borderless contacts in a GL-RMG process, the top portion of spacers that are formed next to the gate will inevitably become compromised during the RMG process, as is known in the art, particularly in a polishing step that is used to open up the gate area in order to remove the dummy gate therein. In addition, work function metal that is deposited during the replacement metal gate process, as well as the metal gate itself will need to be recessed in order to avoid contact with the borderless contact.